Contract Electronic Hardware Design

PO Box 32, Saxapahaw, N.C. 27340 (336)376-3481
Contact: Donald Gerard Polak

8085A Microprocessor Verilog Design for Reuse Course

A short course by Donald Gerard Polak

1. Introduction

Coding for reuse is not some arcane or outdated science like alchemy, nor does it involve some religious sect such as Voodoo. It is, instead, a powerful set of techniques that, when properly employed, allows your code to be used across multiple devices with varying architectures without alteration. A no less important side effect of these techniques is that the physical realization (i.e. fitting and timing closure) becomes easier, resulting in a faster time-to-market. For example, I was able to code, fit, and achieve timing closure of a 1.3 gigabit per second time switch in less than a week. Remember, that when you add value to your employer, your employer will value you.

2. Course Project

Saxelec.com has contracted with Sumuther Manufacturing Company to develop a microprocessor that is instruction set and bus cycle compatible with their existing product line; and yet allow for future expansion. Their current architecture relies on the venerable 8085A microprocessor; invented by Intel™ Corporation with a later, enhanced instruction set version supplied by other vendors. It must be compatible with the existing products and support some high-level languages in use by the embedded developers.

During subsequent negotiations, all parties agreed to use Tundra SemiconductorsCA80C85B and Intel's 8085AH-2 as baseline instruction set and worst case bus timing models, respectively, with the option of disabling the extended instructions and reverting to the 8085AH-2 model during compile. In addition, the following items were agreed upon:
  • The minimum clock cycle frequency as measured at SYSCLK output must be capable of at least 16 MHz in third generation FPGAs.

  • Object code must fit into small to mid-sized FPGAs. The 8085A version (without the enhanced instructions) must fit into new generation CPLDs, with the clock frequency requirements waived.

  • The "Decimal Adjust for Addition" (DAA) instruction should be capable of generating proper results for add, decrement, increment, and subtract operations; with the decimal arithmetic sign of the result reflected within the sign flag.

  • Relative addressing (fixed displacement from a register value) for data is required. Base register may be limited to HL only. Data may be 8-bit values only and the source and destination may be limited to 8-bit data with the accumulator register as the source or destination.

  • Ability to move the contents of the stack pointer register (SP) to the HL register in a single instruction is required if relative addressing from HL only is implemented.

  • Hardware multiply and divide are required. These instructions may consume no more than 14 processor cycles.

  • The move register to itself instructions (MOVE A,A; MOVE B,B; MOVE C,C; MOVE D,D; MOVE E,E; MOVE H,H; and MOVE L,L) do not need to be preserved in an extended instruction set.

  • Unused flags from the original and the CA80C85B processors may be used for any purpose.

  • Global tristate and reset pins are required.

  • For reference this project will be known as the S8085D microprocessor.

Further negotiations with the embedded software development team yielded the following further agreements:

  • Bit 3 of the flag register may be used to designate the type of operation performed. This 'negative flag' (nf) is set for all arithmetic operations involving subtract or decrement and cleared for all other operations that can affect the sign bit.

  • Within the extended instruction set, the MOVE H to H instruction is replaced by one that stores the contents of the accumulator at an address specified by the contents of the HL register plus the contents of the following program byte, with sign extension. Neither the accumulator nor the HL register are affected. No flags are changed.

  • Within the extended instruction set, the MOVE L to L instruction is replaced by one that loads the accumulator from an address specified by the contents of the HL register plus the contents of the following program byte, with sign extension. The HL register is not affected. No flags are changed.

  • Within the extended instruction set, the MOVE D to D instruction is replaced by one that multiplies the contents of the B register by the contents of the C register and stores the result in the combined BC register. The zero, sign, and unsigned indicator flags are affected by the results of this operation. The negative flag is unconditionally cleared.

  • Within the extended instruction set, the MOVE E to E instruction is replaced by one that divides the contents of the BC register pair by the contents of the accumulator. The quotient is stored in the BC register pair and the remainder is stored in the accumulator. The overflow flag is set if the original contents of the accumulator are zero and the operation is aborted. If the accumulator is not zero, the unsigned indicator flag is unconditonally set,the carry, auxiliary carry, sign flag, and negative operation flags are unconditionally cleared; and the remaining flags are adjusted according to the remainder.

  • Within the extended instruction set, the MOVE C to C instruction is replaced by one that duplicates the contents of the stack pointer register in the HL register. The former contents of the HL register are overwritten. No flags are changed.

With this proposed instruction set and existing specifications (i.e. Tundra Semiconductors CA80C85B and Intel's 8085AH-2 as baseline instruction set and worst case bus timing models, respectively, with the option of disabling the extended instructions and reverting to the 8085AH-2 model during compile) the requirement for a customer specification document was waived until project completion.

3. Course Description

This course is setup as four modules of six lessons each. As you study, we will develop a microprocessor intellectual property together to reinforce the skills that you will learn. Each lesson will be available during the period of its 'parent' module. The code we develop will also remain permanently available. A parent module and its subsequent lessons may be replaced periodically by other modules. There are exercises but no quizzes or tests associated with these lessons; although educators or other users may wish to create them.

Module 1 deals with design basics, including coding rules for reuse, design partitioning and architectural development, test bench layout, clock division by odd integers, and the use of parameters and defines.

In Module 2 we start 'fleshing out' the infrastructure modules and study microcode and state machines. By the end of module 2 you will have a microprocessor skeleton that has more than 80% of the instructions coded and able to execute.

Finished instruction listing for module 2

Module 3 finishes the functional coding of our design. Even though we had coded over 80% of the instruction set in module 2, we were left with little more than a programmable logic controller (PLC). In lesson 1 you will learn about simulation techniques, advanced function like CRC generation, and how to use your simulation to debug your code. In lessons two and three we will delve into the functions that set a processor apart from sequencers and controllers. The final three lessons delve into some of the higher arithmetic functions like decimal adjustements, multiply, and divide.

In Module 4 we work on synthesis, timing closure, and certification of our design. We demonstrate synthesis and timing closure using both Xilinx and Altera tool sets. We then fit and acheive timing closure for the selected devices. We now have a 20 Mhz IP ready to use, however it will only fit into FPGAs at this point.

Let's begin

Currently available: Module 1, Module 2, Module 3, Module 4

This page maintained by:

Donald Gerard Polak
@ PHONE (336)376-3481
EMAIL dpolak@emailhosting.com