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8085A Microprocessor IP Verilog Design for Reuse Training Definitions

Definitions

This group of pages refer to many industry terms, specific to the technology, with which you may not be completely familiar. Many of the terms are new, arcane, abbreviated, or contextually misused. However, you may encounter them in your career and will be expected to know them; whether you are a professional, casual browser, or student. I will do my best to define them for you. But, I recommend Wikipedia.com for a more detailed explanation of these terms.

This page is subject to frequent, additions, deletions, expansions, or updates. However, may I suggest only a periodic printout of this page for quick reference; unless you are particularly fond of cluttered desktops.

ASCII  
American Standard Code for Information Interchange. An eight-bit code for representing characters to be displayed.
BIOS  
An acronym for basic I/O system. BIOS provides a low level software interface for many of the devices that are usually connected to a personal computer (PC). It also usually contains the power-on self-test (POST) processes.
BOILERPLATE  
A block of text that is to be inserted as-is into a document, and must not be altered in any way by the document creators. A boilerplate normally contains corporate logos and legal statements to establish document ownership for copyright and patent protections.
A TYPICAL TEXT BOILERPLATE FOR VERILOG MODULES
clock domain  
A clock domain is the group of all signals and synchronous elements whose transitions take place at the edges of one particular (normally periodic) signal.
combinatorial feedback  
A type of circuit where the output of an asynchronous logic block is also fed back as one of its inputs; either alone, or in combination with one or more other signals.
combinatorial logic  
A type of circuit where the sum of products of the inputs is instantly available (ignoring propagation delay) at the output.
common ambiguity  
This is the desired state that should occur on shared busses during driver change-over. It refers to a condition where all potential drivers are simultaneously high impedance. Lack of, or insufficient, common ambiguity causes bus collisions which, in turn, can result in signal integrity issues, reduced product life, and/or potential ground bounce.
CPLD  
An acronym for complex programmable logic devices. CPLDs are non-volatile, programmable logic devices that usually contain a mixed array of logic elements and registers. They are useful in small to mid-sized applications, especially when instant availability is a constraint. Older CPLDs have fairly long propagation delays and may not be suitable for some high-speed applications. Some of the earlier devices also have asymmetric logic, where output pins a fed by logic that has different amount of input terms. This is particularly true with early GAL devices.
DRO  
Digital Read Out. A device that visually displays numeric values, such as a seven segment display.
edge and level sensitive  
A signal that is asserted only when the input signal transitions from an idle to an active state, and remains in the active state until the signal is recognized or reset. Either a transition of the input signal back to its idle state that occurs prior to recognition, or signal recognition will reset this signal to an idle state.
edge sensitive  
A signal that is asserted only when the input signal transitions from its idle to active state, and remains asserted until recognized.
event  

For purposes of the discussions contained in this presentation, an event is a change of state to an input of a design element that either immediately changes, or has the potential to immediately change the state of the output of that same element. For example, changes of state to the 'D' input of a rising edge triggered D flip-flop are not considered an event, whereas the rising edge of the clock is.

Event is also used to describe a change of condition of an external device or internal state, either anticipated or un-anticipated, that requires special handling, and takes precedence over, the normal operational flow or condition of the processor (see interrupt).

exception  

Another name for interrupt.

expander  

A device or module that decodes a set of encoded data into individual signals. This type of device or module is also called a decoder/de-multiplexer.

This term is also used to refer a set of buffers in some CPLD architectures that allows pterms from logic cells to act as separate outputs for reuse by other logic cells.

external event  

The change of condition of an external device, either anticipated or un-anticipated; that requires special handling, and takes precedence over, the normal operational flow or condition of the processor (see interrupt).

fan-in  
Dependent upon device architecture, fan-in can either be the number of physical input signals used by a particular element, or the total number of physical input signals and output signals that are reused by an element (i.e. feedback), to create an output. Note that both a signal and its ones complement are considered to be a single physical input within the context of programmable logic.
fan-out  
The number of physical element inputs driven by one particular element output. Note that both a signal and its ones complement are considered to be a single physical input within the context of programmable logic.
FPGA  
An acronym for field programmable gate array logic. FPGAs are volatile programmable logic devices that contain an array of logic elements and registers. Each cell typically uses a RAM-based lookup table to generate its logic function and the registers have separate inputs and sometimes separate outputs that allows them to be used independent of any logic function that may co-reside in the same cell. FPGAs are configured on power up or command from a ROM that may reside either internal or external to the device package. Most FPGAs are large, relative to CPLDs, and some larger devices approach the typical modern ASIC range. Modern FPGAs frequently feature sophisticated additional functions such as block RAM, delay-locked-loops, phase-locked-loops, multipliers, I/O elements that support various standards, etc. This allows them to be used in a broad range of applications.
GAL  
An acronym for gate array logic. GALs are non-volatile programmable logic devices that contain an array of logic elements. They typically use Gallium-Arsenide technology and have very fast propagation times. They may or may not contain register elements. They are used in very small applications when propagation delay is a constraint.
glitch  

A momentary erroneous condition, inconsistent with the generating logic, that may or may not cause further anomalies. A glitch differs from a bug in the fact that this state is not caused by a logical error in the coding.

Glitches normally occur from 5 primary sources:

  1. Propagation Delay

    Propagation delay is the most frequent cause for glitches. They occur when one or more inputs arrive later than another. Propagation glitches in programmable logic may occur from routing delays or excessive fan-in to the logic generating the culprit signal. In sequential logic, this type of glitch may not present a problem unless the glitch corresponds to a clock signal event.

  2. Skew

    Skew is similar to propagation delay in its effect. However, it varies in the cause. In programmable devices, skew is often caused by routing delays and impedance mismatches.

  3. Ground Bounce

    An extremely damaging condition that can occur even on the dies of programmable devices. Ground bounce occurs when the ground metal layer or any portion thereof briefly rises to a positive potential, relative to other signals. Ground bounce can be caused by lack of I/O balancing, insufficient common ambiguity on bi-directional I/O pads, bad de-coupling, or poor layout. Ground bounce may cause I/O structure damage and poor signal integrity, and can cause random device re-configuration or memory cell alteration. Severe ground bounce and can even lead to latch-up (which can only be mitigated with a fire extinguisher).

  4. Crosstalk

    Crosstalk occurs when another signal source inductively superimposes its image upon the required signal. Crosstalk most frequently occurs from poor routing external to the device package and is propagated inward but can also originate from intense E fields from inductive elements such as transformers and chokes.

  5. Signal Integrity

    Signal integrity issues always arise external to the device and are propagated inward. They arise from EMI, crosstalk, ground bounce, and reflections.

HDL  

An acronym for high-level design language. High-level design languages are a logical, behavioral, or architectural description of a design; rather than the physical implementation of that design.

INSTANCE  

A single copy of a module, function, or primitive with its associated inputs, outputs, and values.

INSTANTIATION  

The process of incorporating a copy of a module, function, or primitive into the project and associating its inputs, outputs, and parameters with particular signals or values.

internal event  

The change of condition of an internal state, either anticipated or un-anticipated, that requires special handling, and takes precedence over the normal operational flow or condition of the processor (see interrupt).

interrupt  

A signal that something has changed with the condition of an external device or internal state that will require special handling outside of, and take precedence over, the normal operational flow of the processor. These signals may occur at regular or sporadic intervals.

interrupt disable  

A signal that will prevent the recognition of any interrupt signal except an NMI.

interrupt enable  

A signal that will enable the recognition of all interrupt signals that have not been otherwise masked.

interrupt mask  

A set of values used to selectively disable the recognition of certain interrupt signals.

Jitter  

A frequency modulation of a periodic signal, or a non-periodic signal whose edges coincide or are controlled by a periodic signal. Jitter is normally expressed as a maximum time amplitude deviation from a periodic signal with no frequency modulation (called unit interval) within a particular range of (modulating) frequencies. The time amplitude deviation is normally expressed as a percentage of the unit interval.

Level sensitive  

A signal whose active state can only be recognized while it remains in that state.

LSb  

An abbreviation for least significant bit.

LSB  

An abbreviation for least significant byte.

metastability  

Metastability is an infrequent condition that happens in register elements when either data or clock enable setup and hold, or clock width or edge constraints are violated. Metastability can exhibit one of three different symptoms. The first symptom, and extremely rare, is when the element output enters a state midway between its high-level output state and low-level output state. This state may appear on instrumentation as a high impedance condition. However, it differs in the fact that the element is actually driving its output rather than that output becoming a high impedance. This could potentially cause physical damage to the device if the condition persists for a long interval. The second symptom that may occur is when the element output oscillates between its high-level output state and low-level output state. The last symptom, and the most frequent, is when the device output begins to enter its expected state, but then returns to its former state. Once entered, a metastable state will persist until the next clock signal event.

microcode  

A sequential series of steps, unique to each instruction, that a microprocessor must execute in order to complete that instruction.

MSb  

An abbreviation for most significant bit.

MSB  

An abbreviation for most significant byte.

nesting  

Allowing an open conditional statement to permit another conditional statement to be opened within its scope. Nesting requires a last-in-first-out approach to statement closure. That is, any conditional statement opened within the scope of another conditional statement must be closed prior to the 'parent' statement closure.

NMI  

An interrupt signal whose recognition cannot be prevented globally, by interrupt disable, or specifically, by use of an interrupt mask.

normalization  

The process of making the positions of the least significant bit of all operands in a multi-operand arithmetic equation correspond by altering the exponents of one or more of the operands.

PAL  

An acronym for programmable array logic. PALs are non-volatile programmable logic devices that contain an array of logic elements, including registers. They are typically very small devices and logic elements may differ in fan-in.

polling  

A hardware or software process that periodically checks the condition of a particular state or signal.

PGA  

An acronym for programmable gate array. PGAs are non-volatile programmable logic devices that typically use a 'sea of logic' approach. The typical PGA frequently uses a 'sum of products' algorithm to synthesize the required logic.

Priority Encoder  

A multiple input, multiple output, asynchronous, logic structure that allows only one output to be active at a time based upon the respective dominance of the active inputs. Priority encoders are frequently used in interrupt controllers, bus arbiters, and other such devices which allow some inputs to override others.

pterm  

Technically this is a concatenation of the words 'product' and 'term'. Modern usage expands its meaning to include the output of any non-registered logic element. Early programmable logic technology relied upon a 'sum of products' approach to logic synthesis (i.e. an 'AND' (product) function followed by an 'OR' function (sum)) in accordance with De-Morgan's theorem. Many of these early and some of the modern devices make the product term available to other elements in the design by use of expanders or other means.

restart  

Another name for interrupt.

RTL  

An acronym for register transfer language. Register transfer languages are a subset of HDLs that describe the logical behavior of a design; rather than the physical implementation of that design.

sequential logic  

A type of circuit where the sum of products of the inputs is not propagated to the output until the occurrence of a specific signal event.

sign extension  

The process of increasing the width of a two's complement number by replicating the value of that number's most significant bit to all added bits.

skew  

Skew is a phenomenon that occurs when the phase of a signal entering one entity does match the phase of that same signal entering another entity. In programmable devices, skew is most often caused by routing delays and impedance mismatches. Modern devices offer closely impedance matched global routing resources for high fan-out signals, such as clocks, to overcome this issue.

subrate  

A signal whose transitions occur at fixed divisions, greater than one, of another signal.

transparent latch  

A type of device which will propagate the input value to the output while its enable is true, and retain the last propagated output value while its enable is false.

UDP  

An acronym for user defined primitive, the UDP is gate level-logic, defined by a user, that features one or more inputs and a single output. The UDP contains a truth table to define the output value for all possible combinations of inputs

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UEFI  

An acronym for universal extensible firmware interface. A low level interface to devices that may be connected to a computer system that allows higher level software to re-vector the handling of particular devices; thereby providing enhanced services.

UNICODE  
A sixteen-bit code for representing characters, with the upper eight bits designating the character set, and the lower eight bits representing the character to be displayed.
This page maintained by:

Donald Gerard Polak
@ PHONE (336)376-3481
EMAIL dpolak@emailhosting.com