Coding for Reuse Course - Module 1 Lesson 5
Clock divisions by an odd number and our timing module

In this lesson we will how to divide a clock signal by an odd number and create the timing module for our microprocessor.

1. Oscillator Constraints


The 8085 series of microprocessors featured an oscillator drive output, X2, to stimulate an external resonant circuit (Parallel tank, crystal, or RC) in order to drive the clock input. This scheme formed a Pierce Oscillator.

A Pierce Oscillator

In the 8085 series of processors, the inverting buffer was an internal component with the buffer input designated as the X1 pin, and the buffer output designated as the X2 pin. In order to retain the ability of using our IP in a CPLD or FPGA on a mezzanine card as a drop in substitute, this buffer must be implemented.

This is not to say that some other changes may be required in the external circuitry. First off, with lower drive capabilities of modern devices, I cannot recommend the tank circuit or RC network as the resonant element. You should use a crystal circuit.

The crystal itself also may need a change. Because internal bypass capacitance may vary more than the physical realizations in programmable devices (based upon device family, layout, pin selection, etc.), the crystal should have a broad "pull range". This requires an AT cut crystal that does not oscillate in the overtone mode, and has a low shunt capacitance, since the bypass to shunt capacitance ratio is critical to the pull range.

Device selection for your target device is also important in regards to pad-to-pad delays. The pad-to-pad delay mathematically cannot exceed 25% of the clock frequency, or the circuit will not oscillate. Allowing a 50% margin for temperature, humidity, and other external factors, the maximum pad-to-pad delay of the driving device cannot be more than 12.5% of the clock period. This constraint is fairly easy to meet with low frequency clocks, for instance a 5 Mhz clock will allow a pad-to-pad delay of 15.6 ns, well within the range of modern devices. But with higher frequency clocks, the Pierce oscillator solution may not function with any available programmable devices.

Because of Rule 3.10, we cannot directly invert to clock input (X1) in order to drive X2. Instead we must first create an image of X1 in order to drive X2 by dividing by 1. The circuit I am about to describe has many other utilizations where the clock image or other odd division is required, for instance, generating strobes.

2. Odd Division Types


There are three fundamental types of circuits that will divide a periodic signal by an odd number. Choice of any of these circuit for a particular project is largely based upon project constraints. For reuse quality, we will emphasize one. The three fundamental types are:

  1. Asymmetric divides. An asymmetric divide will divide one half cycle of the driving clock by ((int)n/2) and the other half by (((int)n/2) + 1). This method will not work when 'n' is less than three. It also severally impacts the duty cycle of the resultant clock, based upon the value of 'n'. For instance, assuming a driving clock with a 50% duty cycle and a divisor of 3, the positive phase at ((int)(3/2) and the negative phase at (((int)3/2) + 1); the resultant clock would only have a 33% duty cycle. This system will also violate Rule 3.10.

  2. Frequency doubling. This method relies on vendor specific architecture of internal phase-locked-loops (PLLs) or delay-locked-loops (DLLs), or external components to double the frequency of the input clock; thereby enabling an even divide of "n x 2". Delay locked loops must be reset if the input clocks vary during operation. I have observed that a reset may not always work if the input clock becomes absent for a period; requiring you to remove and reinstate the device power to correct the problem. You must also be wary of cascading DLLs or PLLs since this condition may also result in phase errors. Finally, this method violates Rule 3.8; but must be considered in very high frequency applications.

  3. Digital Signal Processing. Don't let this scare you. There is a phenomenon that takes place on the 'z' plane unit circle. Let us declare the division value as 'n'. If I divide the input clock by (2 * n) as one signal, phase delay that value by (n / 2) as the other signal, and perform a mod1 addition (EXLUSIVE OR) these two signals, the output signal will be the input divided by 'n' phase delayed by the propagation delays within the logic. Observe the following waveforms for a divide by three circuit:

    This circuit works for all values of 'n', however you target device should support at least '2 * n' frequencies since it requires both clock edges for odd divides.

    There are some techniques you can use to exceed this last specification. I have done this with a very specific device, whose characteristics were well understood. By some miracle, it has never experienced a customer failure in over ten years of high-volume production, and supports a majority of worldwide phone calls. I would not bet upon doing this again in a programmable device, but may be an option in ASICs. I will respond to specific inquiries about this technique, but will not disclose it here to avoid confusion.

    To comply with Rule 2.6, your code should use a separate module for the opposite clock edge when performing odd number divides. If fixed values are used for even number divides, there are more efficient techniques.

    This circuit replicates the time difference in the phases of the duty cycle of the driving clock. Therefore, a divide by one circuit driven by a clock with a duty cycle of 33% will generate a signal that also has a duty cycle of 33%, but a divide by three circuit with the same driving clock would yield a 44% duty cycle.

    Do not be confused by vendor specifications. The 'fmax' parameter, for instance, is useful for calculating shift register performance. It represents a register to register value. If there is intervening logic however, 'fmax' means little. Device targeting requires analyzing the actual circuit and associated delays within a signal path as well as dwell, setup, and hold requirements for that signal. When you are using both clock edges, as in our circuit, metastability is a large concern.

3. Our Timing Module


Before we can code our module, there are a couple of things to remember.

  1. Since our clocks must run continuously, even during resets, we definitely cannot use the device resets within the timing module.

  2. Because of the former limitation, we MUST use an 'initial' block to set the startup conditions for any divide counters or registers. Otherwise, any derived or dependent signals will appear as an unknown ('x') state for the entire simulation.

  3. Division by any odd number requires both clock edges. In our module, we are dividing by one. Therefore, to comply with Rule 2.6, we require a subordinate module for any signal that is clocked on the opposing clock edge.

Using these constraints for the timing module, we can arrive at this new evolution of our project code:

Timing Skeleton

You will probably notice immediately the parameterized 'dreg_r' module that I am using for the phase delay. We will discuss parameterized modules in the next lesson.

I also converted the outputs from all subordinate modules to registers and set initial values to prepare for simulation.

4. Simulation


I will simulate our project with IVERILOG. I am using a 100ns reset width and a 50MHz clock. Initially I set the simulation interval to 100 microseconds. Therefore, I have created the following definition file for the test bench:

Simulation definition file

First I create a directory for simulation. I then copy the source files into that directory and rename them from the command prompt:

ren s8085d_skel1_r.v.txt s8085d_r.v

ren s8085d_t_pre1.v.txt s8085d_t.v

ren s8085d_p_pre1.v.txt s8085d_p.v

ren s8085d_t_d.v.txt s8085d_t_d.v

The simplest way to use IVERILOG is to add the IVERILOG binary path to your system environment PATH variable. You then launch the COMMAND PROMPT and change your directory to your simulation directory. From there enter the following commands:

iverilog -o s8085d_t.out s8085d_t.v

vvp s8085d_t.out -lxt

When vvp encounters the $stop directive it does not automatically exit. Instead, it will present a caret ('>') prompt and await further commands. Enter 'finish' at this prompt to exit vvp.

We can now use GTKWAVE to view the waveform. Enter the following command:

gtkwave s8085d_t.lxt

From the gtkwave window, you can browse and add signals to your display. I only added the clock signals to this display since that is what we are simulating:

GTKWAVE Display of Simulation Results

5. Exercise

  1. Design a divide by seven circuit.

  2. Compare your timing circuit to the one presented here. What could you do better and why?

  3. Your target device has a setup and hold requirement of 2ns, a d to q delay of 1ns, and a logic delay of 4ns, and minimum routing delay of 1ns. the vendor specifies an fmax parameter of 300 MHz. Will this device support your circuit?

  4. Write a test bench for your circuit.

  5. Using some of the available resources compile and simulate your code.