Infrastructure. Coding for Reuse Course - Module 2

Introduction

Now that we have learned some of the basic principles involved in setting up our project and coding for reuse, I'm sure that you're more than ready for a design that does a little more than inverting a clock. By the end of module 2 we will have coded the infrastructure for the basic instructions and learned about state machine development. Moreover, our microprocessor project will be capable of executing some primitive programs.

Architectural Considerations

Let's revisit the project architecture that we developed in Module 1, Lesson 2 for a minute.

Current Block Diagram

We can see that internally we have a sixteen-bit structure from the viewpoint of the source and destination busses. We must keep this in mind when coding our infrastructure. We also know from the design specifications (i.e. Tundra Semiconductors CA80C85B and Intel's 8085AH-2, that we have to support a number of eight-bit registers. This will also affect our infrastructure, but in ways that you may not expect.

Now let's look at our register arrangement:

Register Arrangement

You can see a couple of minor differences between this arrangement and the register file in the Tundra Semiconductors CA80C85B. The increment/decrement/address latch register has been removed, and 16 bit temporary, and accumulator/flags registers added. The reasons for these deviations are simple, although not readily apparent for those of you that have not designed processors before.

There are more efficient ways to perform the increment and decrement functions in programmable logic, which I will go into later. The accumulator and flags registers exist in different places in the earlier models as eight bit registers, but to facilitate the 'PUSHPSW' and 'POPPSW' instructions, a combined register makes more sense. The previous devices also featured an eight-bit temporary register, but for reasons of efficiency our version expands it to sixteen bits. The address latch has been moved in our design to the bus interface block.

There is another register in both the classical and our current design that generally does not appear in the upper level block diagrams. Since the instruction opcode may need to be reference multiple times during the course of instruction execution, the instruction decode and sequencing block must contain an instruction register.

The bus architecture must also be accounted for. The 8085 series processors use an eight-bit external bus. The least significant byte of multi-byte instructions and values occupies the lower address (BIG ENDIAN).

Now that we've refined our architecture a little more, let's enhance our code into a
Processor That Executes Instructions.