Coding for Reuse Course - Module 2 Lesson 3
State Machines and Bus Logic

In this lesson we will study state machines in detail and develop the bus state machine for our microprocessor.

State Machines  

State machines are simply registers whose output value depends upon a value loaded during a certain recurring event, such as a clock edge. There is no requirement for periodicity of this event, some control state machines use asynchronous events as the clock. State machine outputs can be optionally forced to an initial value by another asymmetric event, such as an asynchronous reset or power-up condition. State machine loaded values depend upon its current output value (feedback), and frequently upon other signals. This allows state machines to develop very complex signals.

State machines may be used to control other signals or events that are not an actual part of the state machine, for instance the loading of a register, or a shift. If an event or signal is register based and uses the same clocking event as the state register, it is often coded within the state machine logic so that it can share state decodes with the state machine, reducing logic. This is referred to as an internal state machine, as the state counter is an integral part of the state machine, and cannot alloe the state definitions to change. Other state machines use states that do not directly control the output signls, and must be interpreted. These type of state machines are referred to as eternal state machines. These type of state machines counters can be sysnthesized as ither, more efficient, counter architectures such as Grey code. We generally use external stae machines for very wide outputs with few, or many shared states to reduce decoding logic.

State machines may be depicted with state transition diagrams. Each bubble depicts an individual state. Lines showing state transitions c onnect the bubbles, or may connect to the same bubble. When a signal other than the clock is associated with a particular transition, the connecting line should be labeled with the signal name and value the triggers that particular transition. Very complex state machines generally are broken down, or states consolidated when depicted with state transition diagrams for usability. Complex state machines may also be depicted using flow charts.

State Transition Diagram

State Machine Implementation  

State machine outputs are sometimes connected directly to output signals, preventing possible glitches. However very wide state machines should use coded output values to minimize their width, since each bit in the state machine requires a multiplexer and multiplexer select logic to generate the next loaded value. This logic can quickly use up resources in an FPGA or cause lengthy propagation delays. The number of signals used in addition to the feedback should also be minimized for the same reasons.

State machines can sometimes generate identical outputs for different states. In order for the feedback logic to determine the next state we have to add a set of differentiator bits to the state machine. These bits are only used by the state machine itself.

State machines should be coded with non-blocking assignments and a case statement, referencing the current value, so that current synthesis tools can properly identify and optimize them. The current value should be parameterized in concordance with Rule 6.12 using a name that reflects its intended function or procedure step (Rule 1.3). Since each bit or bit field is significant, I recommend a vertical set of notes above the parameter declarations describing each bit or bit field.

Bus State Machine  

The bus state machine directly controls the ALE, IOM_N, S0, S1, WR_N, RD_N, INTA_N, and HLDA signals. It is also responsible for setting RD_N, WR_N, S0, S1, IOM_N, A[15-8], and AD[7:0] to a high impedance state during DMA operations and reset or power down conditions, and setting the direction for AD[7:0]. For purposes of this discussion, the term cycle refers to a high to low transition of the sysclk signal (i.e. 2 cycles of clk_x1).

To accomplish these tasks, the bus state machine uses request/response logic in conjunction with the instruction decoder/sequencer block to generate the appropriate bus cycle.

There are 10 distinct bus cycles that the bus machine must accommodate:

  1. Bus Idle

    Transitional state between instructions that allows certain instructions to occupy additional cycles when fetched. All outputs are driven to an idle state and DMA is allowed. The bus state machine will naturally assume this state after any instruction fetch unless directed otherwise.

  2. Instruction Fetch

    Identical to a general memory fetch except that S0 is driven to a one, one cycle, is added, and DMA is allowed after RD_N transitions back to high. Internal acknowledgment is sent at start of the cycle after READY is sampled high.

    Instruction Fetch Cycle

  3. Memory Fetch

    IOM_N and S0 are set low. S1 is set high. A[15:8] is set to the value of the upper eight address bits. AD[7:0] is driven to the value of the lower eight address bits for the duration of the first cycle and then set to high impedance. ALE is set high at the beginning of the first cycle at set low at the midway point of the first cycle. RD_N is driven low at the beginning of the second cycle. The READY input is sampled at the midway point of the second cycle, and if it is low, at the midway point of each subsequent cycle until it is sampled high. Acknowledgment is sent at the start of the cycle after READY is sampled high and RD_N driven high at the midway point. Basic Memory fetches (i.e. READY remains high for the entire cycle) require 3 cycles. DMA is not allowed.

    Memory Fetch Cycle

  4. Memory Write

    IOM_N and S1 are set low. S0 is set high. A[15:8] is set to the value of the upper eight address bits. AD[7:0] is driven to the value of the lower eight address bits for the duration of the first cycle and then set to the write data value. ALE is set high at the beginning of the first cycle at set low at the midway point of the first cycle. WR_N is driven low at the beginning of the second cycle. The READY input is sampled at the midway point of the second cycle, and if it is low, at the midway point of each subsequent cycle until it is sampled high. Acknowledgment is sent at the start of the cycle after READY is sampled high and WR_N driven high at the midway point. Basic Memory writes (i.e. READY remains high for the entire cycle) require 3 cycles. DMA is not allowed.

    Memory Write Cycle

  5. Interrupt Autovector Cycle

    Restarts 7.5, 6.5, and 5.5 and TRAP are what is generally termed 'autovector' interrupts. That is, when the interrupt is recognized, the processor begins fetching instructions from a fixed address in memory that is associated with that particular interrupt. Therefore, there is no need to fetch the "CALL" or "RESTART" instruction from the interrupting device. However, the processor does execute cycles that emulate "RESTART" instruction fetches. These cycles are identical to IACK cycles for INTR with a 'RESTART' instruction returned, except that INTA_N and RD_N remain high for the duration of the cycle. DMA is not allowed.

    Interrupt Autovector Cycle

  6. Interrupt Acknowledge Fetch

    Identical to an instruction fetch except that S0, S1, IOM_N, and A[15:8] are all driven high; and INTA_N cycles replace RD_N cycles, and the first interrupt acknowledge requires a minimum of six cycles. AD[7:0] is driven high for the duration of the first cycle. DMA is not allowed. Acknowledgment is sent at start of the cycle after READY is sampled high. DMA is allowed after INTA_N returns to a high.

    Interrupt Acknowledge Cycle (RESTART INSTRUCTION)

  7. Interrupt Acknowledge Read

    If the interrupt acknowledge fetch cycle returns a "CALL" instruction, it is immediately followed by two interrupt acknowledge "read" cycles that are identical to memory fetch cycles except that RD_N remains high for the duration of the cycle, INTA_N replicates the RD_N cycle used in memory fetch cycles, and the address used is 16'hFFFF.

    Interrupt Acknowledge Cycles (CALL INSTRUCTION)

  8. I/O Fetch

    S0 is set low. IOM_N and S1 are set high. A[15:8] is set to the device address. AD[7:0] is driven to the device address for the duration of the first cycle and then set to high impedance. ALE is set high at the beginning of the first cycle at set low at the midway point of the first cycle. RD_N is driven low at the beginning of the second cycle. The READY input is sampled at the midway point of the second cycle, and if it is low, at the midway point of each subsequent cycle until it is sampled high. Acknowledgment is sent at the start of the cycle after READY is sampled high and RD_N driven high at the midway point. DMA is not allowed.

    I/O Fetch Cycle

  9. I/O Write

    S1 is set low. S0 and IOM_N are set high. A[15:8] is set to the device address. AD[7:0] is driven to the device address for the duration of the first cycle and then set to the write data value. ALE is set high at the beginning of the first cycle at set low at the midway point of the first cycle. WR_N is driven low at the beginning of the second cycle. The READY input is sampled at the midway point of the second cycle, and if it is low, at the midway point of each subsequent cycle until it is sampled high. Acknowledgment is sent at the start of the cycle after READY is sampled high and WR_N driven high at the midway point. DMA is not allowed.

    I/O Write Cycle

  10. Bus Wait

    During 10 cycle instructions, the bus must wait an additional six cycles after instruction fetch. During this period, ALE is driven low, IACK_N is driven high, and S0, S1, IOM_N, RD_N, WR_N, AD[7:0], and A[15:8] are all set to high impedance. DMA is allowed.

    Instruction Fetch with Bus Wait Cycle

    Since the bus idle condition is assumed without external intervention, there are only eight cycles that must be directly requested.

Effect of READY  

The READY input is used by peripheral devices to add cycles to the basic bus cycles. These additional cycles are frequently called 'wait' states. The number of wait states corresponds to the number of times READY is sampled low. The READY input is first sampled at the midway point of the second cycle of the bus operation, and if it is low, at the midway point of each subsequent cycle until it is sampled high; at which point the cycle can proceed to completion.

I/O Read with 1 Wait State

Direct Memory Access  

Direct memory access, or DMA, is allowed after RD_N cycles, during an instruction fetch cycle, after INTA_N cycles during the first cycle for an interrupt acknowledge, and anytime during a bus idle. DMA is used by external devices, such as disk drives, to read from, or write to, the processor memory.

DMA is started by an external device asserting HOLD. HOLD is sampled at the start of the cycle following READY being sampled high for instruction fetch and interrupt acknowledge cycles, or continuously during bus idle cycles. If it is sampled high, it is acknowledged one half cycle later by HLDA asserted high. One half cycle later, A[15:8], AD[7:0], S0, S1, IOM_N, RD_N, and WR_N are set to high impedance. HOLD is then sampled at the start of each subsequent cycle until it is sampled low. One cycle later, HLDA is de-asserted and A[15:8], AD[7:0], S0, S1, IOM_N, RD_N, and WR_N driven to their normal states.

Instruction Fetch with DMA

Preliminary Bus State Machine  

Now that we know what it has to do, let's code our preliminary bus state machine:

Skeleton with Preliminary Bus State Machine Added

Note how the cycle requests were coded so that S[1:0] and iom_n could be derived directly from the request instead of requiring addition state machine bits. "rack" was also setup as an independent register since it has only one transition.

Exercise  
  1. What is the most important attribute or attributes of the events that clock a state machine?

  2. What are the ways we can use state machine outputs?

  3. Are all bits in a state machine directly coupled to an output signal?

  4. The next questions pertain to the following problem:

    • IEEE specification 1149.1 (JTAG specification) describes the state machine that all slave devices, called TAP or TAPJ, must use. The TAP is clocked by an event occurring with a single signal, TCLK. The state transitions are controlled by another signal, called TMS. The state machine may be reset asynchronously by a signal called TRST. After TRST is asserted, the state machine assumes the condition "TEST MODE RESET".

      • When the state machine is in the "TEST MODE RESET" condition, it will remain in this state until TMS is low, at which time it enters "RUN TEST IDLE". The TAP will remain in "RUN TEST IDLE" until TMS is high. It will then change to "SELECT DR"..

      • On the following clock event, the state machine will enter either "CAPTURE DR" if TMS is 0 or "SELECT IR" if TMS is 1.

      • If the state machine assumed the "CAPTURE DR" state, the next clock event will cause it to proceed to "EXIT1DR" if TMS is 1, or "SHIFT DR" if TMS is 0. If the state machine entered the "SELECT IR" state, the next clock event will force it to transition to the "CAPTURE IR" state if TMS is 0, or back to the "TEST MODE RESET" state if TMS is 1.

      • The state machine will remain in a "SHIFT DR" state as long as TMS is 0. When TMS becomes 1, it can proceed to the "EXIT1 DR" state. From a "CAPTURE IR", the state machine will either assume a "SHIFT IR" condition if TMS is 0, or an "EXIT1 IR" state if TMS is 0.

      • The "SHIFT IR" state will persist while TMS is a 0. When it becomes 1, the state machine will transition to "EXIT1 IR". From an "EXIT1DR" state, the next state becomes "PAUSE DR" if TMS is 0, or "UPDATE DR" if TMS is 1.

      • "PAUSE DR" state will continue as long as TMS is a 0, when it becomes 1, the state machine will transition to "EXIT2 DR". From an "EXIT1 IR" state, the state will become "PAUSE IR" if TMS is 0, or "UPDATE IR" if TMS is set to 1.

      • When the state machine is in the "EXIT2 DR" condition, the next clock event will force it back to "SHIFT DR" if TMS is 0, or forward to "UPDATE DR" if TMS is 1. A "PAUSE IR" state will persist until TMS becomes 1, at which time the state machine will proceed to "EXIT2 IR".S is 0, or to the "UPDATE IR" state if TMS is 1.

      • On the next clock event, the "EXIT2 IR" state will transition back to the "SHIFT IR" state if TMS is 0, or to the "UPDATE IR" state if TMS is 1

      • The next transition from either "UPDATE DR" or "UPDATE IR" is identical. If TMS is 1 the next state becomes "SELECT DR"; otherwise it becomes "RUN TEST IDLE".

    Draw the state transition diagram for the problem.

  5. Assuming that TMS is sampled on the falling edge of TCLK, write the Verilog code for this state machine.

  6. Use your transition diagram to answer the following: If TMS is forced to a fixed value, what is the value that would return the state machine to "TEST MODE RESET". What is the maximum number of TCLK cycles needed to return to "TEST MODE RESET"