Coding for Reuse Course - Module 3 Review

We finished coding and performed preliminary simulation all versions of our processor in module 3. Let's review what you should have learned.
Summary  

Module 3 introduction began with a brief discussion of the reasons for simulation and using different simulation strategies in iterations. We then talk about the differences and similarities between processors and other forms of sequential logic.

Lesson 1 details some of the simulation strategies, and when they are best used. We then discuss cyclic redundancy checks and how they are generated. We also delve into Verilog functions. Finally, we demonstrate the use of functional simulation to remove errors.

Sub-programs and decision making instructions were discussed in lesson 2. We talked about the role of the flags in making decisions, and which instructions are used for decision making. We also coded and simulated the instructions used to execute and return from a sub-program, the decision making instructions, and the XTHL and HLSP instructions.

Lesson 3 introduced internal and external events and how the processor reacts to them. It discusses interrupt priority and the priority encoder. We detail the interrupt control instructions and interrupt masking. We also look a little deeper into Verilog functions. We finished by coding and simulating the interrupt block and the RESTART instructions.

Lesson 4 dealt with the math involved with decimal adjust for addition and subtraction. We discussed the corner cases we encounter with DAA, hundreds complement notation, and the 'true sign' logic. We completed the coding of the 8085A, 8085B, and 8085C versions of the processor in this lesson.

In Lesson 5 we looked into multiply, and binary multiplication techniques. We studied the basic binary multiplier and the use of Horner's method to reduce logic. We talked about faster multipliers like the Booth multiplier and the use of pipelining to speed up the multiply operation. We also talked about symbol widths and their impact on multiply speeds. Finally, we coded and simulated our multiplier using Horner's method.

Lesson 6 focused on long division and how we implemented it in our processor, without adding excessive logic. We added a new bus cycle type to allow the additional time required to execute long division. We also modified our flag logic to properly update all flags. We coded and simulated the divide instruction, and completed the coding of the S8085D processor version.

Exercise  
  1. Explain Horner's method and how it is used to multiply.

  2. What can happen during a DAA instruction when we add 1 to 99 and how can we mitigate it?

  3. What is meant by an event?

  4. Define a CRC for the generating side.

  5. What kind of divider do we use in our processor?

  6. What do we use for decisions making?

  7. Describe Verilog functions

  8. Draw the timing diagram for an interrupt recognition cycle returning a CALL instruction.