Finishing Touches. Coding for Reuse Course - Module 4


In module 3 we completed the initial coding of our design and simulated most key functions, instructions, or instruction groups. We used Iverilog exclusively during this phase of our project. However, Iverilog is a very forgiving compiler. It does not call out many errors, especially connectivity errors, that can be fatal to synthesis tools. We also must verify that we can meet the timing constraints. Therefore, it is time to target different devices and see if we can build a physical device.

Synthesizing Our Design

When you are developing reusable code, it is, obviously, advantageous to synthesize the code for target devices from more than one company. I checked the websites from the major device vendors. At this writing, Xilinx offers a free, webpack edition of ISE version 14.7 and a free version of their Vivado design suite; Altera offers a free version of their Quartus software (Quartus Lite version 15.1); Lattice Semiconductors offers free versions of Lattice Diamond and IspLever software; and Microsemi offers a free version of their Libero design suite. Of course, the free versions offer limited device support and advanced timing analyzers; but, they are suitable for small designs and our learning exercise.

For this module, I installed Xilinx, ISE version 14.7 webpack, and Altera, Quartus Lite version 15.1. I suggest that you do the same so you can follow along.

Module Structure

In Lesson 1 we begin by creating a project, setting the synthesis options, and synthesizing our design using Xilinx ISE to detect the coding errors that Iverilog may have overlooked. We look at both the errors and warnings and eliminate as many as we can. Finally, we study how to use the detailed synthesis report to find the affected signals and eliminate combinatorial loops.

Lesson 2 creates an Altera project and then takes the code we developed in Lesson 1 and performs synthesis. We then remove the Altera synthesis warnings; which requires the restructuring of our adder. The code changes required to support Altera devices is then re-synthesized with ISE.

Timing closure in both Xilinx and Altera devices is detatiled in Lesson 3. At the completion of this lesson we will have a complete 20 MHz 8085A (B,C,D) microprocessor ready to fit into FPGAs but not CPLDs.

Lesson 4 demonstates some basic techniques for reducing the size of the IP, and fits it into a MAX II CPLD. It also creates code for a version that uses an external state machine for the microcode and a one-hot instruction decoder.