The source and/or object code (subsequently referred to as code)
presented in this and subsequent lessons is the property of
saxelec.com and owner who retains copyright protection. This code in
whole or in part is licensed only for single copy per user,
non-commercial use; except in the case of educational institutions,
where a license of single copy per student, only as part of course
curricula, is permitted.
Donald Gerard Polak (owner)
Starting a "Quartus" Project
Create a directory for your Quartus project and copy the current
source code that we created in
module 4, lesson 1, the
parameter file, and the definitions file into it. Rename these
files to "s8085d_r.v" (source code), "s8085d_p.v"
(parameter file), and "s8085d_d.v" (definitions file). The
install and launch Quartus.
When you launch Quartus for the first time, or on subsequent launches
if you did not check the box to prevent the dialog from opening, you
will see the following dialog:
Quartus Launch Dialog
We want to click on the "New Project Wizard" button. If
you disabled this dialog, you can still get to the wizard by selecting
"New Project Wizard" under the "File" pull
When the new project wizard opens, you may see an introduction
window. It is okay to disable this introduction by checking the
"Don't show me this introduction again" box., if you don't
want it. Then click the "Next" button.
You now get to a window where you can setup the working directory,
the project name, and the top level entity name. Not that the top
level entity name must match the name of the top level module in
our source code. In our case this name is "s8085d_r". The
working directory should match the name of the directory that you
created for your Quartus project. There are no restrictions on
the project name, however, I generally set it to match the top
level entity name for convenience.
Quartus Directory, Project Name, and Top Level Entity Dialog
The working directory is setup with a file bowser or by direct
entry. The project name and top level entity names work the same,
however, if you use the file browser method, you must remove the
period that is appended to the names. When you have entered the
name, click the "Next" button.
The next dialog sets the project type. We want to select
"Empty project" and click the "Next" button.
Quartus Project Type Dialog
Add Files to Your "Quartus" Project
We now arrive at the "Add Files" screen:
Quartus Add Files Dialog
The "File Name" line on this window is setup for keyboard
entry of the pathname to your file, or a standard file browser. To
use the file browser feature, click on the "..." button
next to the line. Either using the keyboard to enter the full pathname
to your source file, or use the file browser to locate and select the
file. Once the file is located, the name will appear on the second
line and the "Add" button will be highlighted. Click on
the "ADD" button. The filename will now appear in the list
of files in the bottom window and is ready to be added to your
project. You may use the "Add All" button to add the source
and included files for those projects where the included files contain
code that can be synthesized. In this project that it not the case,
so use the "Add" button. Once you have added your source
code file(s) click on the "Next" button.
Selecting a Device
We now must select a device to synthesize our project. Because of
the size constraints, we already know that we want a 256-pin FBGA
package. For the cost constraints you generally want to select the
smallest device and slowest speed grade thatcan support your
intellectual property. However, there are a multitude of exceptions,
mostly based upon volumes. Many times particular package types are
popular for specific device sizes and speed grades, thereby reducing
cost. Many companies also negotiate contract pricing for certain
For our project purposes we want to use the Cyclone IV E family, the
smallest of which is the EP4CE6. The 256-pin FBGA package is
denoted by appending F17 to the part number. We want a commercial
temperature profile, so our ideal device will be a EP4CE6F17C8. I
looked up current pricing at Digikey and it came in at single unit
pricing of about $15 USD as of April 2016.
The device selection screen,
Quartus Select Device
features several filter buttons to help you narrow your device search
criteria. Each button will display a dropdown list when clicked on.
By selecting the Cyclone IV E family, the FBGA package, the 256 pin
count, and the eight speed grade with these buttons, we can quickly
locate and select our device. Select the EP4CE6C17C8 device and
click "Next". This will bring up the "EDA Tool
Settings" dialog. Set the simulation tool settings to
"ModelSIM - Altera" and the simulation language to
Once you have completed making your assignments, click the
"NEXT" button. a project summary box will then appear. If
you are satisfied with the summary, click the "FINISH"
button to create your project.
Setting Synthesis Options
Before we can begin synthesis, we need to set certain options.
Because we are using coded fields and direct output signals in
our state machines, we need to set FSM encoding to "User".
There are some other options we want to setup for detailed error and
warning messages, preserving hierarchies, and to increase the
performance of our design.
The settings editor can be accessed in one of two ways. You may
select the "Settings" options under the
"Assignments" pull down menu on the top bar, or you
may highlight "Analysis and Synthesis" in the lower portion
of the left hand window, right click, and select the "Edit
Settings" option. With either option, we get the following
Quartus Settings Menu
Initially we want to use the "Balanced" optimization mode.
I have found that an overly constrained design may exhibit poorer
performance than using minimal guidance. We also want to enable the
"Prevent register merging" checkbox (which will also
automatically select the "Prevent register retiming" option.
You also want to make sure that the "Prevent register
duplication" checkbox is unchecked. Then click on the
"Advanced Settings (Synthesis)..." button. This
will bring up an extensive menu of synthesis options:
Quartus Synthesis Settings Menu
Since there are so many options, we want to initially set all of
them to their default state. To do this, click on the "Reset
All" button. Now we can set the options that we are concerned
with. The setting values are pull down lists that are accessed by
clicking on the current value.
We want to preserve our project hierarchy so we are able to debug
our source code. Consequently, you want to set "Disable
Register Merging Across Hierarchies" to "On" and
"Allow Shift Register Merging across Hierarchies" to
"Off". To obtain the most detailed messages possible, we
set "Analysis & Synthesis Message Level" to
"High" and "HDL message level" to "Level
We want predictable operation between different vendors, so set
"Remove Duplicate Registers" to "Off",
"Restructure Multiplexers" to "Off", and
"State Machine Processing" to "User-Encoded".
For best design optimization, turn "Perform WYSIWYG Primitive
Resynthesis" "On". Once these options are setup,
click the "OK" button. You will return to the compiler
settings window. Click the "OK" button in this window to
return to the main project window.
Now we can run our first synthesis and start removing synthesizer
warnings and errors. We click on the blue right arrow on the
"Analysis & Synthesis" option in the lower portion
of the left hand menu. Once the synthesis runs, the summary report is
displayed in the center of the window:
Quartus Synthesis Flow Summary
We had a successful synthesis run, so let's look for any warnings.
Click on the "Analysis & Synthesis" folder icon
immediately to the left of the flow summary. This will open a list
of available reports. Now we click on either "Messages"
or "Flow Messages" to access messages and warnings.
The warnings are highlighted in blue. We see four warnings. The
first warning can be ignored since it results from using the free
edition of the Quartus software. The second warning comes from a
failure to declare "ie_pending" as a wire in
"int_control_r". The next warning comes from an
incorrect "RESET_VALUE" width on line 3780. The final
warning comes from the Altera megafunction used to replace our 4-bit
adder. The megafunction expects a separate output for carry.
This could be problematic, since we will have to restructure our
adder and still make it fast enough. However, we need the carries
out of each 4-bit element, which limits our ability to use the
standard carry-look-ahead approach.
To minimize delays, we can use eight, 2-bit, carry select adders:
2-Bit Carry Select Adder
For an n-bit carry select adder, the maximum path delay is n/2 + 1
logic elements. Therefore, our adder will have a nine logic element
When we implement these changes we are left with the following source
Updated project source file.
Now, when we rerun the synthesis, we see we are only left with the
warning that comes from our version of Quartus. We also run the
new source through our ISE project and see that we have no
What type of adder are we using? Why?
Download Quartus and create a project.
How can you access the synthesis messages?
What is the maximum logic element delay for an n-bit carry select